- an Information Portal by Dr. Debashish Mohapatra
Title Published Date
A 2:4 Decoder in Dataflow Modelling Tue, 05 Jul 2011
A 3:8 Decoder in Behavioural Modelling using CASE Statement Tue, 05 Jul 2011
A four bit Ripple Carry Adder in Structural Modelling using four Full-Adders as component Tue, 05 Jul 2011
Accumulator Code and Test Bench in VHDL Thu, 08 Nov 2012
Address Decoder Thu, 08 Nov 2012
Binary Coded Decimal (BCD) to Seven Segment Display Behavioural Modelling Tue, 05 Jul 2011
Code for Full-Adder using Dataflow type of modelling Tue, 05 Jul 2011
Code of Half Adder using Dataflow modeling Tue, 05 Jul 2011
Counter VHDL Code and VHDL Test Bench Thu, 08 Nov 2012
Design of a Simple ALU capable of Performing Addition, Subtraction, Anding and Oring of Two 2-bit Vectors Tue, 05 Jul 2011

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