A 2:4 Decoder in Dataflow Modelling

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY dec IS
    PORT (
        a, b, en : IN STD_LOGIC;
        z : OUT STD_LOGIC_vector(3 DOWNTO 0));
END dec;

ARCHITECTURE Behavioral OF dec IS
    SIGNAL abar, bbar : std_logic;
BEGIN
    z(0) <= NOT(abar AND bbar AND en);
    z(1) <= NOT(a AND bbar AND en);
    z(2) <= NOT(abar AND b AND en);
    z(3) <= NOT(a AND b AND en);
    abar <= NOT a;
    bbar <= NOT b;
END Behavioral;