LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fa IS
PORT (
a, b, cin : IN STD_LOGIC;
s, cout : OUT STD_LOGIC);
END fa;
ARCHITECTURE fa_dataflow OF fa IS
BEGIN
s <= a XOR b XOR cin;
cout <= (a AND b) OR(b AND cin) OR (cin AND a);
END fa_dataflow;
Code for Full-Adder using Dataflow type of modelling
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