LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fa IS
    PORT (
        a, b, cin : IN STD_LOGIC;
        s, cout : OUT STD_LOGIC);
END fa;

ARCHITECTURE fa_dataflow OF fa IS

BEGIN

    s <= a XOR b XOR cin;
    cout <= (a AND b) OR(b AND cin) OR (cin AND a);
END fa_dataflow;