A four bit Ripple Carry Adder in Structural Modelling using four Full-Adders as component

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY adder_4bit_rc IS
    PORT (
        a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        s : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
        cout : OUT STD_LOGIC);
END adder_4bit_rc;

ARCHITECTURE struct OF adder_4bit_rc IS
    SIGNAL c : std_logic_vector(4 DOWNTO 0);
    COMPONENT fa IS
        PORT (
            a, b, cin : IN STD_LOGIC;
            s, cout : OUT STD_LOGIC);
    END COMPONENT;
BEGIN
    c(0) <= '0';
    F1 : fa PORT MAP(a(0), b(0), c(0), s(0), c(1));
    F2 : fa PORT MAP(a(1), b(1), c(1), s(1), c(2));
    F3 : fa PORT MAP(a(2), b(2), c(2), s(2), c(3));
    F4 : fa PORT MAP(a(3), b(3), c(3), s(3), c(4));
    cout <= c(4);
END struct;