Counter VHDL Code and VHDL Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY counter IS
    PORT (
        clk : IN std_logic;
        reset : IN std_logic;
        enable : IN std_logic;
        count : OUT std_logic_vector(3 DOWNTO 0)
    );
END counter;

ARCHITECTURE behav OF counter IS
    SIGNAL pre_count : std_logic_vector(3 DOWNTO 0);
BEGIN
    PROCESS (clk, enable, reset)
    BEGIN
        IF reset = '1' THEN
            pre_count <= "0000";
        ELSIF (clk = '1' AND clk'event) THEN
            IF enable = '1' THEN
                pre_count <= pre_count + "1";
            END IF;
        END IF;
    END PROCESS;
    count <= pre_count;
END behav;

VHDL Test bench for the Counter.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;

ENTITY counter_tb IS
END;

ARCHITECTURE counter_tb OF counter_tb IS

    COMPONENT counter
        PORT (
            count : OUT std_logic_vector(3 DOWNTO 0);
            clk : IN std_logic;
            enable : IN std_logic;
            reset : IN std_logic);
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL enable : std_logic := '0';
    SIGNAL count : std_logic_vector(3 DOWNTO 0);

BEGIN

    dut : counter
    PORT MAP(
        count => count,
        clk => clk,
        enable => enable,
        reset => reset);

    clock : PROCESS
    BEGIN
        WAIT FOR 1 ns;
        clk <= NOT clk;
    END PROCESS clock;

    stimulus : PROCESS
    BEGIN
        WAIT FOR 5 ns;
        reset <= '1';
        WAIT FOR 4 ns;
        reset <= '0';
        WAIT FOR 4 ns;
        enable <= '1';
        WAIT;
    END PROCESS stimulus;

    monitor : PROCESS (clk)
        VARIABLE c_str : line;
    BEGIN
        IF (clk = '1' AND clk'event) THEN
            write(c_str, count);
            ASSERT false REPORT TIME'image(now) &
            ": Current Count Value : " & c_str.ALL
            SEVERITY note;
            deallocate(c_str);
        END IF;
    END PROCESS monitor;

END counter_tb;