Code of Half Adder using Dataflow modeling

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ha IS
    PORT (
        a, b : IN STD_LOGIC;
        s, c : OUT STD_LOGIC);
END ha;

ARCHITECTURE ha_dataflow OF ha IS

BEGIN

    s <= a XOR b;
    c <= a AND b;

END ha_dataflow;