Address Decoder

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Decoder IS
    PORT (
        Sel : IN std_logic_vector(2 DOWNTO 0);
        y : OUT std_logic_vector(7 DOWNTO 0)
    );
END ENTITY Decoder;

ARCHITECTURE Behavioral OF Decoder IS
BEGIN
    y <= "00000001" WHEN Sel = "000" ELSE
        "00000010" WHEN Sel = "001" ELSE
        "00000100" WHEN Sel = "010" ELSE
        "00001000" WHEN Sel = "011" ELSE
        "00010000" WHEN Sel = "100" ELSE
        "00100000" WHEN Sel = "101" ELSE
        "01000000" WHEN Sel = "110" ELSE
        "10000000" WHEN Sel = "111";
END ARCHITECTURE Behavioral;

VHDL Test Bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TestDecoder IS
END TestDecoder;

ARCHITECTURE behavior OF TestDecoder IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT Decoder
        PORT (
            Sel : IN std_logic_vector(2 DOWNTO 0);
            y : OUT std_logic_vector(7 DOWNTO 0)
        );
    END COMPONENT;

    --Inputs
    SIGNAL Sel : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
    --Outputs
    SIGNAL y : std_logic_vector(7 DOWNTO 0);
    -- No clocks detected in port list. Replace  below with
    -- appropriate port name
    CONSTANT clock_period : TIME := 10 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut : Decoder PORT MAP(
        Sel => Sel,
        y => y
    );

    -- Stimulus process
    stim_proc : PROCESS
    BEGIN

        WAIT FOR 10 ns;

        sel <= "000";
        WAIT FOR clock_period * 1;
        sel <= "001";
        WAIT FOR clock_period * 1;
        sel <= "010";
        WAIT FOR clock_period * 1;
        sel <= "011";
        WAIT FOR clock_period * 1;
        sel <= "100";
        WAIT FOR clock_period * 1;
        sel <= "101";
        WAIT FOR clock_period * 1;
        sel <= "110";
        WAIT FOR clock_period * 1;
        sel <= "111";

        WAIT;
    END PROCESS;
END;