LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Accumulator IS
PORT (
clk : IN std_ulogic;
inPort : IN std_ulogic_vector(7 DOWNTO 0);
outPort : OUT std_ulogic_vector(7 DOWNTO 0);
enable : IN std_ulogic);
END Accumulator;
ARCHITECTURE Behavioral OF Accumulator IS
SIGNAL sum : std_ulogic_vector(7 DOWNTO 0) := "00000000";
BEGIN
accum_process : PROCESS (clk, enable)
BEGIN
IF (rising_edge(clk) AND enable = '1') THEN
sum <= std_ulogic_vector((unsigned(inPort) + unsigned(sum)));
outPort <= std_ulogic_vector((unsigned(inPort) + unsigned(sum)));
END IF;
END PROCESS accum_process;
END Behavioral;
VHDL Test-bench for Accumulator:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test_Accumulator IS
END test_Accumulator;
ARCHITECTURE behavior OF test_Accumulator IS
COMPONENT accumulator
PORT (
clk : IN std_ulogic;
inPort : IN std_ulogic_vector(7 DOWNTO 0);
enable : IN std_ulogic;
outPort : OUT std_ulogic_vector(7 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_wire : std_ulogic := '0';
SIGNAL inPort : std_ulogic_vector(7 DOWNTO 0);
SIGNAL outPort : std_ulogic_vector(7 DOWNTO 0);
SIGNAL enable : std_ulogic;
BEGIN
uut : accumulator PORT MAP(
clk => clk_wire,
inPort => inPort,
outPort => outPort,
enable => enable
);
--Here we create our clock
clk_wire <= NOT(clk_wire) AFTER 10 ns; -- creating our clock with period 20ns
tb : PROCESS
BEGIN
WAIT FOR 20 ns;
enable <= '1';
inPort <= "00000010";
WAIT FOR 60 ns;
inPort <= "00000100";
WAIT FOR 40 ns;
enable <= '0';
WAIT FOR 60 ns;
WAIT;
END PROCESS;
END;