Design of a Simple ALU capable of Performing Addition, Subtraction, Anding and Oring of Two 2-bit Vectors

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY alu IS
    PORT (
        a, b, s : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        y : OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
END alu;

ARCHITECTURE dataflow OF alu IS

BEGIN

    y <= (a + b) WHEN s = "00" ELSE (a - b) WHEN s = "01" ELSE (a AND b) WHEN s = "10" ELSE (a OR b) WHEN s = "11";

END dataflow;