Summary of Key Features:
The Intel MCS-51 (commonly referred to as 8051) is a Harvard architecture (i.e. it uses different memories for program and data), CISC instruction set (i.e. a single instruction that does many thing that multiple instructions in other computers would do), single chip microcontroller (µC) series which was developed by Intel in 1980 for use in embedded systems.
• Compatible with MCS®-51 Products
• 4K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 10,000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Low-power Idle and Power-down Modes
• Dual Data Pointer
• Fast Programming Time
• Flexible ISP Programming (Byte and Page Mode)
Electrical Characteristics (It’s Limits):
Absolute maximum ratings:
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
8051 Pin Diagram:
Pin-40:- Named as Vcc is the main power source. Usually its +5V DC.
You may note some pins are designated with two signals (shown in brackets).
Pins 32-39: Known as Port 0 (P0.0 to P0.7) – In addition to serving as I/O port, lower order address and data bus signals are multiplexed with this port (to serve the purpose of external memory interfacing). This is a bi directional I/O port (the only one in 8051) and external pull up resistors are required to function this port as I/O.
Pin-31:- ALE aka Address Latch Enable is used to demultiplex the address-data signal of port 0 (for external memory interfacing.) 2 ALE pulses are available for each machine cycle.
Pin-30:- EA/ External Access input is used to enable or disallow external memory interfacing. If there is no external memory requirement, this pin is pulled high by connecting it to Vcc.
Pin- 29:- PSEN or Program Store Enable is used to read signal from external program memory.
Pins- 21-28:- Known as Port 2 (P 2.0 to P 2.7) – in addition to serving as I/O port, higher order address bus signals are multiplexed with this quasi bi directional port.
Pin 20:- Named as Vss – it represents ground (0 V) connection.
Pins 18 and 19:- Used for interfacing an external crystal to provide system clock.
Pins 10 – 17:- Known as Port 3. This port also serves some other functions like interrupts, timer input, control signals for external memory interfacing RD and WR, serial communication signals RxD and TxD etc. This is a quasi bi directional port with internal pull up.
Pin 9:- As explained before RESET pin is used to set the 8051 microcontroller to its initial values, while the microcontroller is working or at the initial start of application. The RESET pin must be set high for 2 machine cycles.
Pins 1 – 8:- Known as Port 1. Unlike other ports, this port does not serve any other functions. Port 1 is an internally pulled up, quasi bi directional I/O port.
Simplified 8051 Architecture:
The system bus connects all the support devices with the central processing unit. 8051 system bus composes of an 8 bit data bus and a 16 bit address bus and bus control signals. From the figure we can understand that all other devices like program memory, ports, data memory, serial interface, interrupt control, timers, and the central processing unit are all interfaced together through the system bus. RxD and TxD (serial port input and output) are interfaced with port 3.
8051 Memory Organization
There are two variations of available memory architecture of 8051. They are Princeton architecture and Harvard architecture. Princeton architecture treats address memory and data memory as a single unit (does not distinguish between two) whereas Harvard architecture treats program memory and data memory as separate entities. Thus Harvard architecture demands address, data and control bus for accessing them separately whereas Princeton architecture does not demand any such separate bus.
Note: 8051 micro controller is based on Harvard architecture while the 8085 is based on Princeton Architecture. .
Thus 8051 has two memories, Program memory and Data memory.
Program memory organization
It has an internal program of 4K size and if needed an external memory can be added (by interfacing ) of size 60K maximum. So in total 64K size memory is available for 8051 micro controller. By default, the External Access (EA) pin should be connected Vcc so that instructions are fetched from internal memory initially. When the limit of internal memory (4K) is crossed, control will automatically move to external memory to fetch remaining instructions. If the programmer wants to fetch instruction from external memory only (bypassing the internal memory), then he must connect External Access (EA) pin to ground (GND).
Data memory organization
In the MCS-51 family, 8051 has 128 bytes of internal data memory and it allows interfacing external data memory of maximum size up to 64K. So the total size of data memory in 8051 can be upto 64K (external) + 128 bytes (internal). Observe the diagram carefully to get more understanding. So there are 3 separations/divisions of the data memory:- 1) Register banks 2) Bit addressable area 3) Scratch pad area.
Register banks form the lowest 32 bytes on internal memory and there are 4 register banks designated bank #0,#1, #2 and #3.
Each bank has 8 registers which are designated as R0,R1…R7. At a time only one register bank is selected for operations and the registers inside the selected bank are accessed using mnemonics R0..R1.. etc.
Other registers can be accessed simultaneously only by direct addressing. Registers are used to store data or operands during executions. By default register bank #0 is selected (after a system reset).
The bit addressable area of 8051 is usually used to store bit variables. The bit addressable area is formed by the 16 bytes next to register banks. They are designated from address 20H to 2FH (total 128 bits). Each bits can be accessed from 00H to 7FH within this 128 bits from 20H to 2FH. Bit addressable area is mainly used to store bit variables from application program, like status of an output device like LED or Motor (ON/OFF) etc. We need only a bit to store this status and using a complete byte addressable area for storing this is really bad programming practice, since it results in wastage of memory.
The scratch pad area is the upper 80 bytes which is used for general purpose storage. Scratch pad area is from 30H to 7FH and this includes stack too.
8051 System Clock
In general cases, a quartz crystal is used to make the clock circuit. The connection is shown in the figure. Clock frequency limits (maximum and minimum) may change from device to device.
Standard practice is to use 12MHz frequency. If serial communications are involved then its best to use 11.0592 MHz frequency.
Let us take a look at the above machine cycle waveform. One complete oscillation of the clock source is called a pulse. Two pulses form a state and six states forms one machine cycle. Also we should note that, two pulses of ALE are available for 1 machine cycle.
8051 Reset Circuit:
8051 can be reset in two ways 1) is power-on reset – which resets the 8051 when power is turned ON and 2) manual reset – in which a reset happens only when a push button is pressed manually. Two different reset circuits are shown above. A reset doesn’t affect contents of internal RAM. For reset to happen, the reset input pin (pin 9) must be active high for at least 2 machine cycles. During a reset operation :- Program counter is cleared and it starts from 00H, register bank #0 is selected as default, Stack pointer is initialized to 07H, all ports are written with FFH.