PRBS( Pseudo Random Binary Sequence Generator) VHDL Code and VHDL Testbench Creation

PRBS Generator:

      Pseudo random binary sequence is essentially a random sequence of binary numbers. So PRBS generator is nothing but random binary number generator.  It is ‘random’ in a sense that the value of an element of the sequence is independent of the values of any of the other elements. It is 'pseudo' because it is deterministic and after N elements it starts to repeat itself, unlike real random sequences. The  implementation  of  PRBS  generator  is  based  on  the  linear  feedback  shift  register (LFSR). The PRBS generator produces a predefined sequence of 1's and 0's, with 1 and 0 occurring with the same probability. A sequence of consecutive n*(2^n -1) bits comprise one data pattern, and this pattern will repeat itself over time.

A PRBS generator is implemented in VHDL, using LFSRs.(Linear feedback Shift Registers which is made up of D-Flip-flops).Here is an example of How it can be done using VHDL.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY dff IS
    PORT (
        CLK : IN std_logic;
        RSTn : IN std_logic;
        D : IN std_logic;
        Q : OUT std_logic);
END dff;

ARCHITECTURE Behavioral OF dff IS
BEGIN
    PROCESS (CLK)
    BEGIN
        IF CLK'event AND CLK = '1' THEN
            IF RSTn = '1' THEN
                Q <= '1';
            ELSE
                Q <= D;
            END IF;
        END IF;
    END PROCESS;
END Behavioral;

VHDL CODE FOR PRBS Generator using LFSR:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY lfsr IS PORT (
    CLK : IN STD_LOGIC;
    RSTn : IN STD_LOGIC;
    data_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END lfsr;
ARCHITECTURE Behavioral OF lfsr IS COMPONENT dff PORT (
    CLK : IN std_logic;
    RSTn : IN std_logic;
    D : IN std_logic;
    Q : OUT std_logic);
END COMPONENT;
SIGNAL data_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL tap_data : std_logic;
BEGIN PROCESS (CLK) BEGIN tap_data <= (data_reg(1) XOR data_reg(2)) XOR (data_reg(4) XOR data_reg(15));
END PROCESS;
stage0 : dff PORT MAP(CLK, RSTn, tap_data, data_reg(0));
g0 : FOR i IN 0 TO 14 GENERATE stageN : dff PORT MAP(CLK, RSTn, data_reg(i), data_reg(i + 1));
END GENERATE;
    data_out <= data_reg AFTER 3 ns;
END Behavioral;

Test Bench Simulation.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testprbs IS END testprbs;
ARCHITECTURE behavior OF testprbs IS
    -- Component Declaration for the Unit Under Test (UUT) 
    COMPONENT lfsr PORT (CLK : IN std_logic;
        RSTn : IN std_logic;
        data_out : OUT std_logic_vector(15 DOWNTO 0));
    END COMPONENT;
    SIGNAL CLK : std_logic := '0';
    SIGNAL RSTn : std_logic := '0';
    SIGNAL data_out : std_logic_vector(15 DOWNTO 0);
    -- Clock period definitions 
    CONSTANT CLK_period : TIME := 10 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT) 
    uut : lfsr PORT MAP(CLK => CLK, RSTn => RSTn, data_out => data_out);
    CLK_process : PROCESS BEGIN CLK <= '0';
        WAIT FOR CLK_period/2;
        CLK <= '1';
        WAIT FOR CLK_period/2;
    END PROCESS;
    -- Stimulus process 
    stim_proc : PROCESS BEGIN WAIT FOR 10 ns;
        WAIT FOR CLK_period * 1;
        RSTn <= '1';
        WAIT FOR CLK_period * 1;
        RSTn <= '0';
        WAIT;
    END PROCESS;
END;