1:8 Multiplexor

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Multiplexer_VHDL IS
    PORT (
        a, b, c, d, e, f, g, h : IN std_logic;
        Sel : IN std_logic_vector(2 DOWNTO 0);

        Output : OUT std_logic
    );
END ENTITY Multiplexer_VHDL;

ARCHITECTURE Behavioral OF Multiplexer_VHDL IS
BEGIN
    PROCESS (a, b, c, d, e, f, g, h, Sel) IS
    BEGIN
        CASE Sel IS
            WHEN "000" => Output <= a;
            WHEN "001" => Output <= b;
            WHEN "010" => Output <= c;
            WHEN "011" => Output <= d;
            WHEN "100" => Output <= e;
            WHEN "101" => Output <= f;
            WHEN "110" => Output <= g;
            WHEN OTHERS => Output <= h;
        END CASE;
    END PROCESS;
END ARCHITECTURE Behavioral;

Test Bench for Multiplexer in VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TextMultiplexer IS
END TextMultiplexer;

ARCHITECTURE behavior OF TextMultiplexer IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Multiplexer
        PORT (
            a : IN std_logic;
            b : IN std_logic;
            c : IN std_logic;
            d : IN std_logic;
            e : IN std_logic;
            f : IN std_logic;
            g : IN std_logic;
            h : IN std_logic;
            Sel : IN std_logic_vector(2 DOWNTO 0);
            Output : OUT std_logic
        );
    END COMPONENT;

    --Inputs
    SIGNAL a : std_logic := '0';
    SIGNAL b : std_logic := '0';
    SIGNAL c : std_logic := '0';
    SIGNAL d : std_logic := '0';
    SIGNAL e : std_logic := '0';
    SIGNAL f : std_logic := '0';
    SIGNAL g : std_logic := '0';
    SIGNAL h : std_logic := '0';
    SIGNAL Sel : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');

    --Outputs
    SIGNAL Output : std_logic;
    -- No clocks detected in port list. Replace  below with
    -- appropriate port name

    CONSTANT clock_period : TIME := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut : Multiplexer PORT MAP(
        a => a,
        b => b,
        c => c,
        d => d,
        e => e,
        f => f,
        g => g,
        h => h,
        Sel => Sel,
        Output => Output
    );

    -- Stimulus process
    stim_proc : PROCESS
    BEGIN
        -- hold reset state for 100 ns.
        WAIT FOR 10 ns;
        a <= '0';
        b <= '1';
        c <= '0';
        d <= '1';
        e <= '0';
        f <= '1';
        g <= '0';
        h <= '1';

        sel <= "000";
        WAIT FOR clock_period * 1;
        sel <= "001";
        WAIT FOR clock_period * 1;
        sel <= "010";
        WAIT FOR clock_period * 1;
        sel <= "011";
        WAIT FOR clock_period * 1;
        sel <= "100";
        WAIT FOR clock_period * 1;
        sel <= "101";
        WAIT FOR clock_period * 1;
        sel <= "110";
        WAIT FOR clock_period * 1;
        sel <= "111";
        WAIT;
    END PROCESS;

END;