4-bit Multiplier Behavioural Modeling

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY FourBitMultiplier IS
    PORT (
        A : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        B : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        Result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END FourBitMultiplier;

ARCHITECTURE Dataflow OF FourBitMultiplier IS

BEGIN

    Result <= std_logic_vector(unsigned(A) * unsigned(B));

END Dataflow;

VHDL Test Bench for 4-Bit Multiplier:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TestFourBitMultiplier IS
END TestFourBitMultiplier;

ARCHITECTURE behavior OF TestFourBitMultiplier IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT FourBitMultiplier
        PORT (
            A : IN std_logic_vector(3 DOWNTO 0);
            B : IN std_logic_vector(3 DOWNTO 0);
            Result : OUT std_logic_vector(7 DOWNTO 0)
        );
    END COMPONENT;

    --Inputs
    SIGNAL A : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
    SIGNAL B : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');

    --Outputs
    SIGNAL Result : std_logic_vector(7 DOWNTO 0);
    -- No clocks detected in port list. Replace  below with
    -- appropriate port name

    CONSTANT clock_period : TIME := 10 ns;

BEGIN

    uut : FourBitMultiplier PORT MAP(
        A => A,
        B => B,
        Result => Result
    );

    stim_proc : PROCESS
    BEGIN
        -- hold reset state for 100 ns.
        WAIT FOR 100 ns;

        A <= "0000";
        B <= "1010";
        WAIT FOR clock_period * 10;

        A <= "1111";
        B <= "1010";
        WAIT FOR clock_period * 10;

        A <= "1111";
        B <= "1111";

        WAIT;
    END PROCESS;

END;