8-Bit Ripple carry Adder

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Adder_8bit IS
    PORT (
        a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        cin : IN std_logic;
        s : OUT std_logic_vector(7 DOWNTO 0);
        cout : OUT STD_LOGIC);
END Adder_8bit;

ARCHITECTURE Structural OF Adder_8bit IS

    SIGNAL c : std_logic_vector(8 DOWNTO 0);

    COMPONENT FullAdder IS
        PORT (
            a, b, cin : IN STD_LOGIC;
            s, cout : OUT STD_LOGIC);
    END COMPONENT;

BEGIN
    c(0) <= cin;
    F1 : FullAdder PORT MAP(a(0), b(0), c(0), s(0), c(1));
    F2 : FullAdder PORT MAP(a(1), b(1), c(1), s(1), c(2));
    F3 : FullAdder PORT MAP(a(2), b(2), c(2), s(2), c(3));
    F4 : FullAdder PORT MAP(a(3), b(3), c(3), s(3), c(4));
    F5 : FullAdder PORT MAP(a(4), b(4), c(4), s(4), c(5));
    F6 : FullAdder PORT MAP(a(5), b(5), c(5), s(5), c(6));
    F7 : FullAdder PORT MAP(a(6), b(6), c(6), s(6), c(7));
    F8 : FullAdder PORT MAP(a(7), b(7), c(7), s(7), c(8));
    cout <= c(8);

END Structural;

VHDL Test Bench for Full Adder:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY TestRippleCarryAdder IS
END TestRippleCarryAdder;

ARCHITECTURE behavior OF TestRippleCarryAdder IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Adder_8bit
        PORT (
            a : IN std_logic_vector(7 DOWNTO 0);
            b : IN std_logic_vector(7 DOWNTO 0);
            cin : IN std_logic;
            s : OUT std_logic_vector(7 DOWNTO 0);
            cout : OUT std_logic
        );
    END COMPONENT;

    --Inputs
    SIGNAL a : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
    SIGNAL b : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
    SIGNAL cin : std_logic := '0';

    --Outputs
    SIGNAL s : std_logic_vector(7 DOWNTO 0);
    SIGNAL cout : std_logic;
    -- No clocks detected in port list. Replace  below with
    -- appropriate port name

    CONSTANT clock_period : TIME := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut : Adder_8bit PORT MAP(
        a => a,
        b => b,
        cin => cin,
        s => s,
        cout => cout
    );

    -- Stimulus process
    stim_proc : PROCESS
    BEGIN
        -- hold reset state for 100 ns.
        WAIT FOR 10 ns;
        a <= "00000000";
        b <= "00000001";
        cin <= '0';
        WAIT FOR clock_period * 1;
        a <= "00000001";
        b <= "00000001";
        cin <= '0';
        WAIT FOR clock_period * 1;
        a <= "00000000";
        b <= "00000001";
        cin <= '1';
        WAIT FOR clock_period * 1;
        a <= "00000001";
        b <= "00000001";
        cin <= '1';
        WAIT FOR clock_period * 1;
        a <= "11111111";
        b <= "11111111";
        cin <= '0';
        WAIT FOR clock_period * 1;
        a <= "11111111";
        b <= "11111111";
        cin <= '1';
        WAIT FOR clock_period * 1;
        a <= "00001010";
        b <= "01010101";
        cin <= '1';
        -- insert stimulus here

        WAIT;
    END PROCESS;

END;