LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY gray_to_binary IS
    PORT (
        g : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END gray_to_binary;

ARCHITECTURE dataflow OF gray_to_binary IS

BEGIN

    b(0) <= g(0) XOR g(1) XOR g(2) XOR g(3);
    b(1) <= g(1) XOR g(2) XOR g(3);
    b(2) <= g(2) XOR g(3);
    b(3) <= g(3);

END dataflow;