A 2-Bit Adder to 7-Segment Display

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY add_to_ssd IS
    PORT (
        a, b : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        y : OUT STD_LOGIC_vector (6 DOWNTO 0));
END add_to_ssd;

ARCHITECTURE Hybrid OF add_to_ssd IS

    COMPONENT fa
        PORT (
            a, b, cin : IN STD_LOGIC;
            s, cout : OUT STD_LOGIC);
    END COMPONENT;

    SIGNAL r : std_logic_vector(2 DOWNTO 0);
    CONSTANT cin : std_logic := '0';
    SIGNAL c : std_logic;

BEGIN
    a1 : fa PORT MAP(a(0), b(0), cin, r(0), c);
    a2 : fa PORT MAP(a(1), b(1), c, r(1), r(2));

    y <= "1111110" WHEN r = "000" ELSE
        "0110000" WHEN r = "001" ELSE
        "1101101" WHEN r = "010" ELSE
        "1111001" WHEN r = "011" ELSE
        "0110011" WHEN r = "100" ELSE
        "1011011" WHEN r = "101" ELSE
        "1011111" WHEN r = "110" ELSE
        "1110000" WHEN r = "111";

END Hybrid;