LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux_4x1_mixed IS
PORT (
a, b, c, d, s0, s1 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux_4x1_mixed;
ARCHITECTURE mixed OF mux_4x1_mixed IS
COMPONENT or4x1 PORT (p, q, r, s : IN std_logic;
t : OUT std_logic);
END COMPONENT;
SIGNAL s0bar, s1bar, t1, t2, t3, t4 : std_logic;
BEGIN
PROCESS (s0, s1)
BEGIN
s0bar <= NOT(s0);
s1bar <= NOT(s1);
END PROCESS;
t1 <= s0bar AND s1bar AND a;
t2 <= s1bar AND s0 AND b;
t3 <= s1 AND s0bar AND c;
t4 <= s0 AND s1 AND d;
G1 : or4x1 PORT MAP(t1, t2, t3, t4, y);
END mixed;
