LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux4x1_if_else IS
    PORT (
        a, b, c, d : IN STD_LOGIC;
        s : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        y : OUT STD_LOGIC);
END mux4x1_if_else;

ARCHITECTURE Behavioral_if_else OF mux4x1_if_else IS

BEGIN
    PROCESS (s, a, b, c, d)
    BEGIN
        IF (s = "00") THEN
            y <= a;
        ELSIF (s = "01") THEN
            y <= b;
        ELSIF (s = "10") THEN
            y <= c;
        ELSE y <= d;
        END IF;
    END PROCESS;
END Behavioral_if_else;