4:1 Mux Modelling using When-Else Statements

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux4x1_when_else IS
    PORT (
        a, b, c, d : IN STD_LOGIC;
        s : IN std_logic_vector (1 DOWNTO 0);
        y : OUT STD_LOGIC);
END mux4x1_when_else;

ARCHITECTURE mux4x1_when_else_modeling OF mux4x1_when_else IS

BEGIN
    y <= a WHEN s = "00" ELSE
        b WHEN s = "01" ELSE
        c WHEN s = "10" ELSE
        d;

END mux4x1_when_else_modeling;