4:1 Mux Dataflow Modelling

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux4x1 IS
    PORT (
        a, b, c, d, s0, s1 : IN STD_LOGIC;
        y : OUT STD_LOGIC);
END mux4x1;

ARCHITECTURE mux4x1_dataflow OF mux4x1 IS

BEGIN

    y <= ((NOT s0) AND (NOT s1) AND a) OR ((NOT s1) AND s0 AND b) OR (s1 AND (NOT s0) AND c) OR (s0 AND s1 AND d);

END mux4x1_dataflow;