Structural Modelling of a 4:1 mux using Three 2:1 mux As components

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux4x1_struct IS
    PORT (
        a, b, c, d, s0, s1 : IN STD_LOGIC;
        y : OUT STD_LOGIC);
END mux4x1_struct;

ARCHITECTURE struct_2mux OF mux4x1_struct IS

    COMPONENT mux2x1 IS
        PORT (
            a, b, s : IN STD_LOGIC;
            y : OUT STD_LOGIC);
    END COMPONENT;
    SIGNAL t1, t2 : std_logic;
BEGIN
    m1 : mux2x1 PORT MAP(a, b, s0, t1);
    m2 : mux2x1 PORT MAP(c, d, s0, t2);
    m3 : mux2x1 PORT MAP(t1, t2, s1, y);

END struct_2mux;