2:1 Multiplexor Dataflow modelling

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux2x1 IS
    PORT (
        a, b, s : IN STD_LOGIC;
        y : OUT STD_LOGIC);
END mux2x1;

ARCHITECTURE mux2x1_dataflow OF mux2x1 IS

BEGIN
    y <= (NOT(s) AND a) OR(s AND b);

END mux2x1_dataflow;