Full adder in Structural modelling using two Half adders and an Or gate as components

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fa_str IS
    PORT (
        a, b, cin : IN STD_LOGIC;
        s, cout : OUT STD_LOGIC);
END fa_str;

ARCHITECTURE fa_struct OF fa_str IS

    COMPONENT ha
        PORT (
            a, b : IN std_logic;
            s, c : OUT std_logic);
    END COMPONENT;

    COMPONENT or21
        PORT (
            a, b : IN std_logic;
            y : OUT std_logic);
    END COMPONENT;

    SIGNAL t1, t2, t3 : std_logic;

BEGIN
    h1 : ha PORT MAP(a, b, t2, t1);
    h2 : ha PORT MAP(t2, cin, s, t3);
    h3 : or21 PORT MAP(t1, t3, cout);
END fa_struct;