CMOS Inverter transient analysis:
Cpar1 out 0 C=6.39989f
Cpar2 gnd 0 C=5.6143587f
Cpar3 vdd 0 C=5.864075f
M1 gnd in out gnd NMOS L=700n W=1.05u AD=3.61375p PD=8.05u AS=4.165p PS=9.1u $ (16.5 18 18.5 21)
M2 vdd in out vdd PMOS L=700n W=1.05u AD=3.61375p PD=8.05u AS=4.165p PS=9.1u $ (16.5 34.5 18.5 37.5)
.include BSIM_50.md
vdd vdd gnd 3.3
vin in gnd pulse(0 3.3 0 .1n .1n 3n 6n)
.tran 1n 40n
.print tran in out
.END
CMOS VTC Spice Code:
Cpar1 gnd 0 C=9.7190887f
Cpar2 vdd 0 C=13.96059f
Cpar3 out 0 C=10.836289f
M1 out in vdd vdd PMOS L=700n W=3.15u AD=9.1875p PD=12.6u AS=9.1875p PS=12.6u
M2 out in gnd gnd NMOS L=700n W=1.05u AD=3.61375p PD=8.05u AS=3.61375p PS=8.05u
.include BSIM_50.md
.model nmos nmos
.model pmos pmos
vin in gnd 1.8
vdd vdd gnd 1.8
.dc vin 0 1.8 .01
.print dc v(out)
.END
2-i/p NAND Transient Analysis:
M1 Out In1 Vdd Vdd PMOS L=700n W=3.15u AD=5.145p PD=6.65u AS=9.1875p PS=12.6u $ (73 18 75 27)
M2 Vdd In2 Out Vdd PMOS L=700n W=3.15u AD=9.1875p PD=12.6u AS=5.145p PS=6.65u $ (83 18 85 27)
M3 6 In1 Gnd Gnd NMOS L=700n W=2.1u AD=2.94p PD=4.9u AS=4.41p PS=8.4u $ (73 -4 75 2)
M4 Out In2 6 Gnd NMOS L=700n W=2.1u AD=4.41p PD=8.4u AS=2.94p PS=4.9u $ (83 -4 85 2)
.include BSIM_50.md
Vdd Vdd gnd 1.8
VIn1 In1 gnd pulse(0 1.8 0 .1n .1n 3n 6n)
VIn2 In2 gnd pulse(0 1.8 0 .1n .1n 6n 12n)
.tran 1n 40n
.print In1 In2 Out
.END
2-i/p NOR Transient Analysis:
M1 Out In2 N1 Vdd PMOS L=700n W=3.15u AD=5.145p PD=6.65u AS=9.1875p PS=12.6u $ (73 18 75 27)
M2 N1 In1 Vdd Vdd PMOS L=700n W=3.15u AD=9.1875p PD=12.6u AS=5.145p PS=6.65u $ (83 18 85 27)
M3 out In1 Gnd Gnd NMOS L=700n W=2.1u AD=2.94p PD=4.9u AS=4.41p PS=8.4u $ (73 -4 75 2)
M4 Out In2 Gnd Gnd NMOS L=700n W=2.1u AD=4.41p PD=8.4u AS=2.94p PS=4.9u $ (83 -4 85 2)
.include BSIM_50.md
Vdd Vdd gnd 1.8
VIn1 In1 gnd pulse(0 1.8 0 .1n .1n 3n 6n)
VIn2 In2 gnd pulse(0 1.8 0 .1n .1n 6n 12n)
.tran 1n 40n
.print In1 In2 Out
.END
2-I/P OR Gate:
.include BSIM_50.md
*.model nmos nmos
*.model pmos pmos
Mn1 out a gnd gnd NMOS L=700n W=2.1u
Mn2 out b Gnd gnd NMOS L=700n W=2.1u
Mp1 N1 a Vdd vdd PMOS L=700n W=3.15u
Mp2 out b N1 vdd PMOS L=700n W=3.15u
Mp3 outab out vdd vdd PMOS L=700n W=3.15u
Mn3 outab out Gnd gnd NMOS L=700n W=2.1u
vdd vdd gnd 5V
va a gnd pulse(0 5 0n .1n .1n 4n 8n)
vb b gnd pulse(0 5 0n .1n .1n 8n 16n)
.tran 1n 100n
.print tran v(a) v(b) v(outab)
.op
2-I/P XOR Gate:
.include BSIM_50.md
M1 BBAR B Vdd Vdd PMOS L=700n W=3.15u AD=9.1875p PD=12.6u AS=9.1875p PS=12.6u
M2 3 BBAR Out Vdd PMOS L=700n W=6.3u AD=8.82p PD=9.1u AS=8.82p PS=9.1u
M3 Out ABAR 3 Vdd PMOS L=700n W=6.3u AD=8.82p PD=9.1u AS=8.82p PS=9.1u
M4 Vdd A 3 Vdd PMOS L=700n W=6.3u AD=15.435p PD=17.5u AS=8.82p PS=9.1u
M5 3 B Vdd Vdd PMOS L=700n W=6.3u AD=8.82p PD=9.1u AS=15.435p PS=17.5u
M6 ABAR A Vdd Vdd PMOS L=700n W=3.15u AD=9.1875p PD=12.6u AS=9.1875p PS=12.6u
M7 Gnd B BBAR Gnd NMOS L=700n W=1.05u AD=4.7775p PD=9.1u AS=4.7775p PS=9.1u
M8 Gnd BBAR 10 Gnd NMOS L=700n W=2.1u AD=4.41p PD=8.4u AS=2.94p PS=4.9u
M9 10 ABAR Out Gnd NMOS L=700n W=2.1u AD=2.94p PD=4.9u AS=2.205p PS=4.2u
M10 Out A 9 Gnd NMOS L=700n W=2.1u AD=2.205p PD=4.2u AS=3.3075p PS=5.25u
M11 9 B Gnd Gnd NMOS L=700n W=2.1u AD=3.3075p PD=5.25u AS=4.41p PS=8.4u
M12 Gnd A ABAR Gnd NMOS L=700n W=1.05u AD=4.7775p PD=9.1u AS=4.7775p PS=9.1u
*********************************STIMULUS******************************************************
.param pow = '3.3'
.param rt = '1n'
.param ft = '1n'
v0 Vdd Gnd pow
v1 A GND PULSE (0 pow 0 rt ft 10n 20n)
v2 B GND PULSE (0 pow 0 rt ft 17n 35n)
***********************************************************************************************
.tran 0.1n 80n
.print tran v(A) v(B) v(Out)
.END