MOSFET (Metal Oxide Semiconductor Field Effect Transistors)
The two types of MOSFETs are the depletion type and the enhancement type, and each has a n / p – channel type. The depletion type is normally on, and operates as a JFET (refer to Figure 2). The enhancement type is normally off, which means that the drain to source current increases as the voltage at the gate increases. No current flows when no voltage is supplied at the gate (refer to Figure 3).
Complementary metal–oxide–semiconductor (CMOS) (pronounced /ˈsiːmɒs/) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication.
CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminum was once used but now the material is polysilicon.
CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits.
The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal–oxide–semiconductor field-effect transistors to create paths to the output from either the voltage source or ground. When a path to output is created from the voltage source, the circuit is said to be pulled up. The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential.
Working: CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied
The image below shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor is in an off (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an on (low resistance) state, allowing the output to drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.
In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this opposite behavior of input and output, the CMOS circuits' output is the inversion of the input.
Duality
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.
More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, then both transistors must have low resistance to the corresponding supply voltage, modeling an AND. When a path consists of two transistors in parallel, then either one or both of the transistors must have low resistance to connect the supply voltage to the output, modeling an OR.
The CMOS Process for an Inverter:
First of all, however, we have to see how we would make one. There is a fundamental problem in trying to use both n-channel and p-channel devices in the same circuit. What is it? It would seem we need two different kinds of substrates, both a p-type substrate for the n-channel transistor, and an n-type substrate for the p-channel device. There is a way around this problem by making what is called a tank or a moat. A moat is a relatively deep region of one type of material placed into a host substrate of the opposite type(Figure 3). We can put n-type source/drain regions into the p-substrate and p-type source/drain regions into the n-moat. In Figure 4, we will also show the gates, and how the whole inverter is connected together.
Now let's draw the schematic (Figure 5): A p-channel device is drawn just like an n-channel device, except we put a little "bubble" on the gate to signify that it is a MOSFET of a different color. Although we usually don't do this all the time, we have also shown the substrate connections in this diagram. These connections show that a MOSFET is at least a four terminal device, not a three terminal one as people often assume. Since, in a p-channel device, the substrate is n-type, we show the substrate connection as an outward pointing arrow. The p-type substrate for the n-channel device is shown as an inward pointing arrow. The n-channel substrate is connected to ground, the p-channel substrate is connected to Vdd. Note that since the n-moat is at Vdd and the p-substrate is at ground, the moat-substrate p-n junction is reverse biased, and so no current should flow between them.
We usually do not label the source and drain either, but we do here, just for completeness. Note that unlike the bipolar transistor, the FET is truly a symmetric device. There is really no way to tell the source from the drain. By convention, we call the element which is connected to the substrate (or moat) the source, and the other the drain. You will sometimes hear the region under the gate (either substrate or moat) referred to as the backbody.
Now let's see how this circuit works. If VIN is high (at or near Vdd) the NMOS transistor will be turned on. The voltage between the gate and substrate of the p-channel device is at or near zero. The gate is at Vdd and so is the moat! Hence the upper transistor will be turned off. The output will thus be low.
If the input voltage is at or near ground (a "low") then the n-channel device is turned off. The voltage between the gate and substrate of the p-channel device is now -Vdd. (The gate is at 0 and the substrate is at +Vdd.) If the PMOS transistor has a threshold voltage VT of, say, -2 V, then it will be turned on and the output will be high. Note however, that in either state, high or low, there is no static current flowing through the inverter.
CMOS Switching Actions:
CMOS Inverter working explanation:
CMOS NOR
The output is low whenever one or both of the inputs is high, and high otherwise.
The MOSFETs act as switches. When one of the inputs is high, the corresponding n-MOSFETs switches on to connect the output to ground. If both inputs are low, the p-MOSFETs switch on to connect the output to +5V.
CMOS NAND
The output is low whenever both inputs are high, and high otherwise.
The MOSFETs act as switches. When both inputs are high, the n-MOSFETs switch on to connect the output to ground. If either input is low, the path to ground is cut off, and one of the p-MOSFETs switch on to connect the output to +5V.
CMOS NAND2 Gate
CMOS NOR2 Gate
CMOS NAND GATE IMPLEMENTATION
CMOS XOR Gate:
Note: Due to the complemented nature of the output of C-MOS logic we are actually using the design logic of XNOR for XOR and vice versa for a simpler circuit.
OBSERVE CAREFULLY
CMOS XNOR
CMOS Logic Cascades:
